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block diagram 1 may 1997 ml2281, ml2282 * , ml2284 # , ml2288 # serial i/o 8-bit a/d converters with multiplexer options general description the ml2281 family are 8-bit successive approximation a/d converters with serial i/o and configurable input multiplexers with up to 8 input channels. all errors of the sample-and-hold, incorporated on the ml2281 family are accounted for in the analog-to-digital converters accuracy specification. the voltage reference can be externally set to any value between gnd and v cc , thus allowing a full conversion over a relatively small voltage span if desired. the ml2281 family is an enhanced double polysilicon cmos pin compatible second source for the adc0831, adc0832, adc0834, and adc0838 a/d converters. the ml2281 series enhancements are faster conversion time, true sample-and-hold function, superior power supply rejection, improved ac common mode rejection, faster digital timing, and lower power dissipation. all parameters are guaranteed over temperature with a power supply voltage of 5v 10%. features n conversion time: 6s n total unadjusted error: 1/2lsb or 1lsb n sample-and-hold: 375ns acquisition n 2, 4 or 8-input multiplexer options n 0 to 5v analog input range with single 5v power supply n operates ratiometrically or with up to 5v voltage reference n no zero or full-scale adjust required n ml2281 capable of digitizing a 5v, 40khz sine wave n low power: 12.5mw max n superior pin compatible replacement for adc0831, adc0832, adc0834, and adc0838 n analog input protection: 25ma (min) per input n now in 8-pin soic package (ml2281, ml2282) input shift-register output shift-register shunt regulator control and timing di sars clk cs do 4-bit se dgnd v+ v cc v ref agnd common ch7 ch6 ch5 ch4 ch3 ch2 ch1 ch0 a/d converter with sample & hold function multiplexer (ml2288 shown) s v ref clk cs v inC successive approximation register d/a converter + C output shift-register control and timing comp a/d with sample & hold function 8pf 8pf C + v in+ v cc gnd do ml2281 ml2288 (8-channel se or 4-channel diff multiplexer) ml2284 (4-channel se or 2-channel diff multiplexer) ml2284 (2-channel se or 1-channel diff multiplexer) (* indicates part is obsolete) (# indicates part is end of life as of july 1, 2000)
ml2281, ml2282, ml2284, ml2288 2 pin configuration cs v in+ v inC gnd v cc clk do v ref 1 2 3 4 8 7 6 5 top view top view cs v in+ v inC gnd v cc clk do v ref 1 2 3 4 8 7 6 5 top view cs ch0 ch1 gnd v cc (v ref ) clk do di 1 2 3 4 8 7 6 5 top view v+ cs ch0 ch1 ch2 ch3 dgnd v cc di clk sars do v ref agnd 1 2 3 4 5 6 7 14 13 12 11 10 9 8 ml2281 single differential input 8-pin dip ml2282 2-channel mux 8-pin dip ml2281 8-pin soic ml2282 8-pin soic ml2284 14-pin soic ch0 ch1 ch2 ch3 ch4 ch5 ch6 ch7 com dgnd v cc v+ cs di clk sars do se v ref agnd 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 top view ml2288 8-channel mux 20-pin dip cs di clk sars do ch3 ch4 ch5 ch6 ch7 910111213 ch2 ch1 ch0 v cc v+ com dgnd agnd v ref se 4 5 6 7 8 3212019 18 17 16 15 14 top view top view v+ cs ch0 ch1 ch2 ch3 dgnd v cc di clk sars do v ref agnd 1 2 3 4 5 6 7 14 13 12 11 10 9 8 ml2284 4-channel mux 14-pin dip ml2288 8-channel mux 20-pin pcc cs ch0 ch1 gnd v cc (v ref ) clk do di 1 2 3 4 8 7 6 5 top view
ml2281, ml2282, ml2284, ml2288 3 name function v cc positive supply. 5v 10% dgnd digital ground. 0 volts. all digital inputs and outputs are referenced to this point. agnd analog ground. the negative reference voltage for a/d converter. ch0-7, analog inputs. digitally selected to be single v in +, v in C ended (v in ) or; v in + or v in C of a differential input. analog range = gnd - v in - v cc . com common reference point for analog inputs. a/d conversion is performed on voltage difference between analog input and this common reference point if single-end conversion is specified. v ref reference. the positive reference voltage for a/d converter. se shift enable. input controls whether lsb first bit stream is shifted out on serial output do. if se = 1, msb first is shifted out only. if se = 0, an msb first bit stream is shifted out, then a second bit stream with lsb first is shifted out after end of conversion. v+ input to the shunt regulator. pin description name function do data out. digital output which contains result of a/d conversion. the serial data is clocked out on falling edges of clk. sars successive approximation register status. digital output which indicates that a conversion is in progress. when sars goes to 1, the sampling window is closed and conversion begins. when sars goes to 0, conversion is completed. when cs = 1, sars is in high impedance state. clk clock. digital input which clocks data in on di on rising edges and out on do on falling edges. also used to generate clocks for a/d conversion. di data input. digital input which contains serial data to program the mux and channel assignments. cs chip select. selects the chip for multiplexer and channel assignment and a/d conversion. when cs = 1, all digital outputs are in high impedance state. when cs = 0, normal a./d conversion takes place.
ml2281, ml2282, ml2284, ml2288 4 electrical characteristics unless otherwise specified, t a = t min to t max , v cc = v ref = 5v 10%, and f clk = 1.333mhz. ml228xb ml228xc typ typ symbol parameter conditions min note 3 max min note 3 max units converter and multiplexer characteristics total unadjusted v ref = v cc (notes 4, 6) 1/2 1 lsb error reference input (notes 4, 7) 10 15 20 10 15 20 k w resistance common-mode (notes 4, 8) gnd v cc gnd v cc v input range C0.05 +0.05 C0.05 +0.05 dc common-mode common mode voltage 1/16 1/4 1/16 1/4 lsb error voltage gnd to v cc/2 (note 5) ac common-mode common mode voltage 1/4 1/4 lsb error gnd to v cc/2 , 0 to 50khz (note 5) dc power supply v cc = 5v 10% 1/32 1/4 1/32 1/4 lsb sensitivity v ref - v cc +0.1v (note 5) ac power supply 100mv p-p , 25khz sine 1/4 1/4 lsb sensitivity on v cc (note 5) change in zero 15ma into v+ 1/2 1/2 lsb error from v cc =5v v cc = n.c. v ref = 5v to internal zener (note 5) operation v z internal diode 15ma into v+ 6.9 6.9 v regulated break- down (at v+) v+ input resistance (note 4) 20 35 20 35 k w absolute maximum ratings absolute maximum ratings are those values beyond which the device could be permanently damaged. absolute maximum ratings are stress ratings only and functional device operation is not implied. current into v+ ...................................................... 15ma supply voltage, v cc ................................................. 6.5v voltage logic inputs ........................................... C7 to v cc +7v analog inputs ................................ C0.3v to v cc +0.3v input current per pin (note 1) .............................. 25ma storage temperature ................................ C65c to 150c package dissipation at t a = 25c (board mount) ............................. 800mw lead temperature (soldering 10 sec.) dual-in-line package (molded) .......................... 260c dual-in-line package (ceramic) ......................... 300c molded chip carrier package vapor phase (60 sec.) ..................................... 215c infrared (15 sec.) ............................................. 220c operating conditions supply voltage, v cc ............................ 4.5v dc to 6.3v dc temperature range (note 2) ................. t min - t a - t max ml2281/2/4/8 bix .................................. C40c to 85c ml2281/2/4/8 cix ml2281/2/4/8 bcx .................................... 0c to 70c ml2281/2/4/8 ccx
ml2281, ml2282, ml2284, ml2288 5 electrical characteristics (continued) ml228xb ml228xc typ typ symbol parameter conditions min note 3 max min note 3 max units converter and multiplexer characteristics (continued) i off off channel on channel = v cc C1 C1 a leakage current off channel = 0v (notes 4, 9) on channel = 0v +1 +1 a off channel = v cc (notes 4, 9) i on on channel on channel = 0v C1 C1 a leakage current off channel = v cc (notes 4, 9) on channel = v cc +1 +1 a off channel = 0v (notes 4, 9) digital and dc characteristics v in(1) logical 1 (note 4) 2.0 2.0 v input voltage v in(0) logical 0 (note 4) 0.8 0.8 v input voltage i in(1) logical 1 input v in = v cc (note 4) 1 1 a current i in(0) logical 0 input v in = 0v (note 4) C1 C1 a current v out(1) logical 1 i out = C2ma (note 4) 4.0 4.0 v output voltage v out(0) logical 0 i out = 2ma (note 4) 0.4 0.4 v output voltage i out hi-z output v out = 0v (note 4) C1 C1 a current v out = v cc 11a i source output source v out = 0v (note 4) C6.5 C6.5 ma current i sink output sink current v out = v cc (note 4) 8.0 8.0 ma i cc supply current ml2281, ml2284 1.3 2.5 1.3 2.5 ma ml2288 (note 4) ml2282 includes ladder 1.8 3.5 1.8 3.5 ma current (note 4)
ml2281, ml2282, ml2284, ml2288 6 electrical characteristics (continued) typ limit symbol parameter conditions min note 3 max units ac electrical characteristics f clk clock frequency (note 4) 10 1.333 khz t acq sample-and-hold acquisition 1/2 1/f clk t c conversion time not including mux adddressing time 8 1/f clk snr signal to noise ratio v in = 40khz, 5v sine. f clk = 1.333mhz 47 db ml2281 (f sampling ? 120khz). noise is sum of all nonfundamental components up to 1/2 of f sampling (note 11) thd total harmonic distortion v in = 40khz, 5v sine. f clk = 1.333mhz C60 db ml2281 (f sampling ? 120khz). thd is sum of 2, 3, 4, 5 harmonics relative to fundamental (note 11) imd intermodulation distortion v in = f a + f b . f a = 40khz, 2.5v sine. C60 db ml2281 f b = 39.8khz, 2.5v sine, f clk = 1.333mhz (f sampling ? 120khz). imd is (f a + f b ), (f a C f b ), (2f a + f b ), (2f a C f b ), (f a + 2f b ), (f a C 2f b ) relative to fundamental (note 11) clock duty cycle (notes 4, 10) 40 60 % t set-up cs falling edge or data input (note 4) 130 ns valid to clk rising edge t hold data input valid after (note 4) 80 ns clk rising edge t pd1 , clk falling edge to output c l = 100pf (note 4 & 12) t pd0 data valid data msb first 90 200 ns data lsb first 50 110 ns t 1h , rising edge of cs to data c l = 10pf, r l = 10k (see high impedance 40 90 ns t 0h output and sars hi-z test circuits) (note 5) c l = 100pf, r l = 2k (note 4) 80 160 ns c in capacitance of logic input 5 pf c out capacitance of logic outputs 5 pf note 1: when the input voltage (v in ) at any pin exceeds the power supply rails (v in < gnd or v in > v cc ) the absolute value of current at that pin should be limited to 25ma or less. note 2: 0c to 70c and C40c to +85c operating temperature range devices are 100% tested with temperature limits guaranteed by 100% testing, sampling, or by correlation with worst-case test conditions. note 3: typicals are parametric norm at 25c. note 4: parameter guaranteed and 100% production tested. note 5: parameter guaranteed. parameters not 100% tested are not in outgoing quality level calculation. note 6: total unadjusted error includes offset, full-scale, linearity, multiplexer and sample-and-hold errors. note 7: cannot be tested for ml2282. note 8: for v in C 3 v in + the digital output code will be 0000 0000. two on-chip diodes are tied to each analog input (see block diagram) which will fo rward conduct for analog input voltages one diode drop below ground or one diode drop greater than the v cc supply. be careful, during testing at low v cc levels (4.5v), as high level analog inputs (5v) can cause this input diode to conductespecially at elevated temperatures, and cause errors for analog input s near full-scale. the spec allows 50mv forward bias of either diode. this means that as long as the analog v in or v ref does not exceed the supply voltage by more than 50mv, the output code will be correct. to achieve an absolute 0v to 5v input voltage range will therefore require a minimum supply voltage of 4.950v dc over temperature variations, initial tolerance and loading. note 9: leakage current is measured with the clock not switching. note 10: a 40% to 60% clock duty cycle range insures proper operation at all clock frequencies. in the case that an available cl ock has a duty cycle outside of these limits, the minimum time the clock is high or the minimum time the clock is low must be at least 300ns. the maximum time the clock can be h igh or low is 60s. note 11: because of multiplexer addressing, test conditions for the ml2282 would be v in = 34khz, 5v sine (f sampling ? 102khz); ml2284 v in = 32khz, 5v sine (f sampling ? 95khz); ml2288 v in = 30khz, 5v sine (f sampling ? 89khz). note 12: since data, msb first, is the output of the comparator used in the successive approximation loop, an additional delay i s built in (see block diagram) to allow for comparator response time.
ml2281, ml2282, ml2284, ml2288 7 v cc data output c l c l r l data output t 1h t 0h t 1h t 0h cs v cc gnd v oh gnd 50% 10% 90% t 1h 90% do and sars outputs cs do and sars outputs gnd v cc v cc v ol 10% t 0h 50% 10% 90% t r t r r l figure 1. high impedance test circuits and waveforms clk clk cs do t set-up t pd0, t pd1 t set-up t set-up t hold t hold cs data in (di) clk data out (do) se t set-up start conversion bit 7 (msb) bit 6 t pd0, t pd1 figure 2. timing diagrams data input timing data output timing ml2281 start conversion timing
ml2281, ml2282, ml2284, ml2288 8 clock (clk) chip select ( cs ) data out (do) clock (clk) chip select ( cs ) data in (di) data out (do) hi-z address mux output data lsb first data msb first data start bit sgl/ dif odd/ sign *lsb first output not available on ml2281 hi-z hi-z hi-z sample & hold acquisition (t acq ) sample & hold acquisition (t acq ) 1 76 5432 10 * (msb) 7654 321 123456 (msb) 7 (msb) 0 (lsb) (lsb) 234567891011 1234567891011121314151617181920 t c t set-up t set-up dont care (di disabled until next conversion cycle) clock (clk) chip select ( cs ) data in (di) data out (do) sar status (sars) address mux output data lsb first data msb first data start bit sgl/ dif select bit 1 odd/sign hi-z hi-z hi-z hi-z sample & hold acquisition (t acq ) 765432 0 12345 (msb) 67 (msb) 1 (lsb) 1234567891011121314151617181920 a/d conversion in process t set-up dont care (di disabled until next conversion cycle) ml2281 timing ml2282 timing ml2284 timing figure 2. timing diagrams (continued)
ml2281, ml2282, ml2284, ml2288 9 clock (clk) chip select ( cs ) data in (di) do using se to control lsb first output sar status (sars) se = 0 data out (do) address mux output data lsb first data msb first data start bit sgl/ dif select bit 1 odd/ sign select bit 0 hi-z hi-z hi-z hi-z hi-z hi-z sample & hold acquisition (t acq ) 765432 0 1234 5 (msb) 67 (msb) 1 (lsb) 1234567891011121314151617181920212223242526 a/d conversion in process data held lsb first data msb first data (lsb) (msb) (msb) 7654321 0 1234567 t set-up t set-up dont care (di disabled until next conversion cycle) se ? ? y ? ? t ml2288 timing figure 2. timing diagrams (continued) 1.0 0.75 0.5 0.25 0 linearity error (lsb) clock frequency (mhz) 0 0.01 0.1 1 v cc = 5v v ref = 5v 125 c C55 c 25 c figure 3. linearity error vs f clk
ml2281, ml2282, ml2284, ml2288 10 1 0.75 0.5 0.25 0 linearity error (lsb) v ref (v dc ) 0235 4 1 v cc = 5v f clk = 1.333mhz 125 c C55 c 25 c figure 4. linearity error vs v ref voltage 1 0.75 0.5 0.25 0 offset error (lsb) v ref (v dc ) 0235 4 1 v cc = 5v v in = 0v f clk = 1.333mhz t a = 25 c figure 5. unadjusted offset error vs v ref voltage
ml2281, ml2282, ml2284, ml2288 11 *some of these functions/pins are not available with other options. note 1: for the ml2284 di is input directly to the d input of select 1. select 0 is forced to a 1. for the ml2282, di is inpu t directly to the d input of odd/sign. select 0 is forced to a 1 and select 1 is forced to a 0. figure 6. ml2288 functional block diagram c q r d r d c q d c q r d c q r + C C + analog mux (equivalent) s 1 ch0* 16 clk 17 di* 18 cs ch1* ch6* v ref v cc v+* dgnd* agnd* 2 ch2 3 ch3 4 ch4* 5 ch5* 6 7 ch7* 8 com* 9 12 20 to internal circuitry 7v shunt regulator input protectionall logic inputs c c r ladder and decoder sar logic and latch 9-bit shift register comp b7 b6 b5 b4 14 do b2 b3 b1 b0 cs cs cs comp parallel xfr to shift register msb first lsb first eoc eoc r r c cs deoc cs se* cs cs cs t d v cc v cc to internal circuits input 13 16 17 18 mux address note 1 13 sars* 15 note 1 select 0 select 1 start rrrr r d c sgl/ dif 5-bit shift-register odd/ sign time delay dstart 2 start dstart 1
ml2281, ml2282, ml2284, ml2288 12 functional description multiplexer addressing the design of these converters utilizes a sample data comparator structure which provides for a differential analog input to be converted by a successive approximation routine. the actual voltage converted is always the difference between an assigned + input terminal and a C input terminal. the polarity of each input terminal of the pair being converted indicates which line the converter expects to be the most positive. if the assigned + input is less than the C input, the converter responds with an all zeros output code. a unique input multiplexing scheme has been utilized to provide multiple analog channels with software configurable single ended, differential, or pseudo differential options. the pseudo differential option will convert the difference between the voltage at any analog input and a common terminal. one converter package can now accommodate ground referenced inputs and true differential inputs as well as signals with some arbitrary reference voltage. a particular input configuration is assigned during the mux addressing sequence, prior to the start of a conversion. the mux address selects which of the analog inputs are to be enabled and whether this input is single ended or differential. in the differential case, it also assigns the polarity of the analog channels. differential inputs are restricted to adjacent channel pairs. for example, channel 0 and channel 1 may be selected as a different pair but channel 0 or channel 1 cannot act differentially with any other channel. in addition to selecting the differential mode, the sign may also be selected. channel 0 may be selected as the positive input and channel 1 as the negative input or vice versa. this programmability is illustrated by the mux addressing codes shown in tables 1, 2, and 3. the mux address is shifted into the converter via the di input. since the ml2281 contains only one differential input channel with a fixed polarity assignment, it does not require addressing. the common input line on the ml2288 can be used as a pseudo differential input. in this mode, the voltage on the com pin is treated as the C input for any of the other input channels. this voltage does not have to be analog ground; it can be any reference potential which is common to all of the inputs. this feature is most useful in single supply applications where the analog circuitry may be biased at a potential other than ground and the output signals are all referred to this potential. since the input configuration is under software control, it can be modified, as required, at each conversion. a channel can be treated as a single-ended, ground referenced input for one conversion; then it can be reconfigured as part of a differential channel for another conversion. figure 7 illustrates these different input modes. m ux address analog single-ended channel# sgl/ odd/ select dif sign 1 001234567com 1000+ C 1001 + C 1010 + C 1011 + C 1100+ C 1101 + C 1110 + C 1111 +C single-ended mux mode m ux address analog differential channel-pair# sgl/ odd/ select 0123 dif sign 1 0 0 1234567 0000+C 0001 +C 0010 +C 0011 +C 0100C+ 0101 C+ 0110 C+ 0111 C+ differential mux mode table 1. ml2288 mux addressing 8 single-ended or 4 differential channels m ux address channel# sgl/ odd/ select dif sign 1 0123 10 0 + 10 1 + 11 0 + 11 1 + single-ended mux mode m ux address channel# sgl/ odd/ select dif sign 1 0123 00 0 + C 00 1 + C 01 0 C + 01 1 C + differential mux mode com is internally tied to agnd table 2. ml2284 mux addressing 4 single-ended or 2 differential channel
ml2281, ml2282, ml2284, ml2288 13 digital interface the block diagram and timing diagrams in figures 2-5 illustrate how a conversion sequence is performed. a conversion is initiated when cs is pulsed low. this line must me held low for the entire conversion. the converter is now waiting for a start bit and its mux assignment word. a clock is applied to the clk input. on each rising edge of the clock, the data on di is clocked into the mux address shift register. the start bit is the first logic 1 that appears on the di input (all leading edge zeros are ignored). after the start bit, the device clocks in the next 2 to 4 bits for the mux assignment word. when the start bit has been shifted into the start location of the mux register, the input channel has been assigned and a conversion is about to begin. an interval of 1/2 clock period is used for sample & hold settling through the selected mux channels. the sar status output goes high at this time to signal that a conversion is now in progress and the di input is ignored. the do output comes out of high impedance and provides a leading zero for this one clock period. when the conversion begins, the output of the comparator, which indicates whether the analog input is greater than or less than each successive voltage from the internal dac, appears at the do output on each falling edge of the clock. this data is the result of the conversion being shifted out (with msb coming first) and can be read by external logic or p immediately. after 8 clock periods, the conversion is completed. the sar status line returns low to indicate this 1/2 clock cycle later. the serial data is always shifted out msb first during the conversion. after the conversion has been completed, the data can be shifted out a second time with lsb first, depending on level of se input. for the case of ml2288, if se = 1, the data is shifted out msb first during the conversion only. if se is brought low before the end of conversion (which is signalled by the high to low transition of sars), the data is shifted out again immediately after the end of conversion; this time lsb first. if se is brought low after end of conversion, the lsb first data is shifted out on falling edges of clock after se goes low. for ml2282 and 2284, se is internally tied low, so data is shifted out msb first, then shifted out a second time lsb first at end of conversion. for ml2281, se is internally tied high, so data is shifted out only once msb first. all internal registers are cleared when the cs input is high. if another conversion is desired, cs must make a high to low transition followed by address information. the di input and do output can be tied together and controlled through a bidirectional p i/o bit with one connection. this is possible because the di input is only latched in during the mux addressing interval while the do output is still in the high impedance state. m ux address channel# sgl/ dif odd/sign 0 1 10 + 11 + single-ended mux mode table 3. ml2282 mux addressing 2 single-ended or 1 differential channel m ux address channel# sgl/ dif odd/sign 0 1 00 + C 01 C + differential mux mode 0 1 2 3 4 5 6 7 + + + + + + + + com (C) 8 single-ended 0 1 2 3 4 5 6 7 + + + + + + + + com (C) 8 pseudo-differential + v bias 0, 1 2, 3 4, 5 6, 7 + (C) C (+) + (C) C (+) + (C) C (+) + (C) C (+) 4 differential 0, 1 2, 3 + C C + + + + + com (C) mixed mode + v bias 4 5 6 7 figure 7. analog input multiplexer functional options for ml2288
ml2281, ml2282, ml2284, ml2288 14 reference the voltage applied to the reference input to these converters defines the voltage span of the analog input (the difference between v in max and v in min ) over which the 256 possible output codes apply. the devices can be used in either ratiometric applications or in systems requiring absolute accuracy. the reference pin must be connected to a voltage source capable of driving the reference input resistance, typically 10k. this pin is the top of a resistor divider string used for the successive approximation conversion. in a ratiometric system, the analog input voltage is proportional to the voltage used for the a/d reference. this voltage is typically the system power supply, so the v ref pin can be tied to v cc . this technique relaxes the stability requirements of the system reference as the analog input and a/d reference move together maintaining the same output code for a given input condition. for absolute accuracy, where the analog input varies between specific voltage limits, the reference pin can be biased with a time and temperature stable voltage source. the maximum value of the reference is limited to the v cc supply voltage. the minimum value, however, can be quire small to allow direct conversion of inputs with less than 5v of voltage span. particular care must be taken with regard to noise pickup, circuit layout and system error voltage sources when operating with a reduced span due to the increased sensitivity of the converter. analog inputs and sample/hold an important feature of the ml2281 family of devices is that they can be located at the source of the analog signal and then communicate with a controlling p with just a few wires. this avoids bussing the analog inputs long distances and thus reduces noise pickup on these analog lines. however, in some cases, the analog inputs have a large common mode voltage or even some noise present along with the valid analog signal. the differential input of these converters reduces the effects of common mode input noise. thus, if a common mode voltage is present on both + and C inputs, such as 60hz, the converter will reject this common mode voltage since it only converts the difference between + and C inputs. the ml2281 family have a true sample and hold circuit which samples both + and C inputs simultaneously. this simultaneous sampling with a true s/h will give common mode rejection and ac linearity performance that is superior to devices where the two input terminals are not sampled at the same instant and where true sample and hold capability does not exist. thus, the ml2281 family of devices can reject ac common mode signals from dc-50khz as well as maintain linearity for signals from dc-50khz. the signal at the analog input is sampled during the interval when the sampling switch is closed prior to conversion start. the sampling window (s/h acquisition time) is 1/2 clk period wide and occurs 1/2 clk period before do goes from high impedance to active low state. when the sampling switch closes at the start of the s/h acquisition time, 8pf of capacitance is thrown onto the analog input. 1/2 clk period later, the sampling switch is opened and the signal present at the analog input is stored. any error on the analog input at the end of the s/h acquisition time will cause additional conversion error. care should be taken to allow adequate charging or settling time from the source. if more charging or settling time is needed to reduce these analog input errors, a longer clk period can be used. the ml2281x family has improved latchup immunity. each analog input has dual diodes to the supply rails, and a minimum of 25ma (100ma typically) can be injected into each analog input without causing latchup. dynamic performance signal-to-noise-ratio signal-to-noise ration (snr) is the measured signal-to-noise at the output of the converter. the signal is the rms magnitude of the fundamental. noise is the rms sum of all the nonfundamental signals up to half the sampling frequency. snr is dependent on the number of quantization levels used in the digitization process; the more levels, the smaller the quantization noise. the theoretical snr for a sine wave is given by snr = (6.02n + 1.76)db where n is the number of bits. thus for ideal 8-bit converter, snr = 49.92db. harmonic distortion harmonic distortion is the ratio of the rms sum of harmonics to the fundamental. total harmonic distortion (thd) of the ml2281 series is defined as thd vvvv v = +++ ? ? ? 20 2 2 3 2 4 2 5 2 1 log where v 1 is the rms amplitude of the fundamental and v 2 , v 3 , v 4 , v 5 are the rms amplitudes of the individual harmonics. intermodulation distortion with inputs consisting of sine waves at two frequencies, f a and f b , any active device with nonlinearities will create distortion products, of order (m + n), at sum and difference frequencies of mf a + nf b , where m, n = 0, 1, 2, 3 . intermodulation terms are those for which m or n is not equal to zero. the (imd) intermodulation distortion specification includes the second order terms (f a + f b ) and (f a C f b ) and the third order terms (2f a + f b ), (2f a C f b ), (f a + 2f b ) and (f a C 2f b ) only.
ml2281, ml2282, ml2284, ml2288 15 zero error adjustment the zero of the a/d does not require adjustment. if the minimum analog input voltage value, v in min is not ground, a zero offset can be done. the converter can be made to output 00000000 digital code for this minimum input voltage by biasing any v in C input at this v in min value. this utilizes the differential mode operation of the a/d. the zero error of the a/d converter relates to the location of the first riser of the transfer function and can be measured by grounding the v in C input and applying a small magnitude positive voltage to the v in + input. zero error is the difference between the actual dc input voltage which is necessary to just cause an output digital code transition from 00000000 to 00000001 and the ideal 1/2 lsb value (1/2 lsb = 9.8mv for v ref = 5.000v dc ). full-scale adjustment the full-scale adjustment can be made by applying a differential input voltage which is 1-1/2 lsb down from the desired analog full-scale voltage range and then adjusting the magnitude of the v ref input or v cc for a digital output code which is just changing from 11111110 to 11111111. adjustment for an arbitrary analog input voltage range if the analog zero voltage of the a/d is shifted away from ground (for example, to accommodate an analog input signal which does not go to ground), this new zero reference should be properly adjusted first. a v in + voltage which equals this desired zero reference plus 1/2 lsb current limiting resistor, i+ 15ma 12v v cc v+ gnd i + ? 28.8k 3.2k 3.2k figure 8. shunt regulator i+ 15ma v+ 5.5v slope = 6.9v 1 35k figure 9. i-v characteristic of the shunt regulator (where the lsb is calculated for the desired analog span, 1 lsb = analog span/256) is applied to selected + input and the zero reference voltage at the corresponding C input should then be adjusted to just obtain the 00000000 to 00000001 code transition. the full-scale adjustment should be made by forcing a voltage to the v in + input which is given be: v fs adjust v vv in max max min +=- - ? ? 15 256 . () where v max = high end of the analog input range v min = low end (offset zero) of the analog range the v ref or v cc voltage is then adjusted to provide a code change from 11111110 to 11111111. shunt regulator a unique feature of ml2288 and ml2284 is the inclusion of a shunt regulator connected from v+ terminal to ground which also connects to the v cc terminal (which is the actual converter supply) through a silicon diode as shown in figure 8. when the regulator is turned on, the v+ voltage is clamped at 11v be set by the internal resistor ratio. the typical i-v of the shunt regulator is shown in figure 9. it should be noted that before v+ voltage is high enough to turn on the shunt regulator (which occurs at about 5.5v), 35k w resistance is observed between v+ and gnd. when the shunt regulator is not used, v+ pin should be either left floating or tied to gnd. the temperature coefficient of the regulator is C22mv/c.
ml2281, ml2282, ml2284, ml2288 16 applications 8051 interface and controlling software mnemonic instruction start anl p1, #0f7h ;select a/d (cs = 0) mov b, #5 ;bit counter ? 5 mov a, #addr ;a ? mux bit loop 1: rrc a ;cy ? address bit jc one ;test bit ;bit = 0 zero: anl p1, #0feh ;di ? 0 sjmp cont ;continue ;bit = 1 one: orl p1, #1 ;d1 ? 1 cont: acall pulse ;pulse sk 0 ? 1 ? 0 djnz b, loop 1 ;continue until done acall pulse ;extra clock for sync mov b, #8 ;bit counter ? 8 loop 2: acall pulse ;pulse sk 0 ? 1 ? 0 mov a, p1 ;cy ? do rrc a rrc a mov a, c ;a ? result rlc a ;a(0) bit ? and shift mov c, a ;c ? result djnz b, loop 2 ;continue until done reti ;pulse subroutine pulse: orl p1, #04 ;sk ? 1 nop ;delay anl p1, #0fbh ;sk ? 0 ret ch0 ml2288 8051 p1 3 p1 2 p1 1 p1 0 cs clk di do ch7
ml2281, ml2282, ml2284, ml2288 17 applications (continued) 10k w clk clk clk clk qd clock generator clk clr clk clk clk int clk cs sars gnd si a si b clk q h v cc v cc v cc sin shift/ load v ref q a 10k w 5 v dc start start + close to start the a/d conversion 0.01 m f 0.001 m f output shift register 74hc164 analog inputs parallel inputs mux address gnd input shift register 74hc165 ml2288 114 1 14 20 19 10 11 12 13 17 d1 com 9 1 2 3 4 5 6 7 8 18 16 15 nc 0 1 2 3 1k w (8) 1/8 v cc 4 5 6 7 do do do v+ dgnd agnd se +10 m f 51k w 2 3 4 5 6 10 11 12 13 7 8 1.3k w (8) 1/2 74hc74 msb data display lsb 5v dc 5v dc 5v dc 5v dc 5v dc (or v in ) 14 nc 10 7 7 6 5 4 3 14 13 12 51k w (4) 11 15 2 1 9 nc sgl/ dif start bit ml2288 stand-alone or evaluation circuit
ml2281, ml2282, ml2284, ml2288 18 3k w + 10 m f ml2281 lm335 t a v in (C) v in (+) v cc v cc (5 v dc ) v ref 10k w t a min adj. 10k w t a max adj. low-cost remote temperature sensor
ml2281, ml2282, ml2284, ml2288 19 applications (continued) 10k w fs adj. 1k w gain 10k w offset dual dual 5.1v 2.7k w 10k w 10v 10v 6.8k w 330 w v cc (5v dc ) 1k w 2v dc zero adj. + + 10 m f 1.2k w 2.7k w 330 w 1k w 3v v in (+) v in v cc v cc v ref Cin +in do clk cs ml2281 v ref ml2281 + 1 m f set voltage span 1m w v in (C) sets zero code voltage + C + C 1m w 20k w 20k w strain gauge load cell 300 w /30mv fs ch0 ch7 serial i/o com lm335 lm385 tl064 tl064 tl064 v ref t ref t ref v cc v cc v cc ml2288 + C + C + C + C + C 910 w 820 w 1k w 1k w type j type j t 1 + C + C t 8 1k w 22k w 88.2k w 88.2k ? ? ? ? uses one more wire than load cell itself two mini-dips could be mounted inside load cell for digital output transducer electronic offset and gain trims relax mechanical specs for gauge factor and offset low level cell output is converted immediately for high noise immunity t ref uses the pseudo-differential mode to keep the differential inputs constant with changes in reference temperature (t ref ) 2k w 3k w 20k w 1k w zero-shift and span adjust: 2v - v in - 5v digital load cell convert 8 thermocouples with only one cold-junction compensator
ml2281, ml2282, ml2284, ml2288 20 applications (continued) obtaining 9-bit resolution v cc v in v in (+) v in (C) v cc v cc (5v dc ) C15v dc 15v dc v ref + C + C + C ml2281 + C C 2.5v > 2.5v + r r ( ( ml2281 + + 10 m f op amp 600 w 1 m f v in (C) v in (+) v cc v ref v cc (5v dc ) v cc (5v dc ) ml2281 load lm336 9.1k w 240k w 120k w 100 w 0.1 w (2a full-scale) i load 2k w 1k w fs adj. 10k w fs adj. 100 w zero adj. + 10 m f ?? + C v in (+) *v in (C) = 0.15v cc 15% of v cc v xdr 85% of v cc v cc v ref v cc (5v dc ) ml2281 0.7 v cc 1k w fs adj. 1k w zero adj. 24k w + 10 m f + 1 m f v cc (5v dc ) + + 10 m f 10k w 2k w 20k w 3k w v in (C)* xdr v xdr + C v in (+) v in v cc v ref ml2281 + 1 m f set for 3v v in (C) controller performs a routine to determine which input polarity provides a non-zero output code. this information provides the extra bits. diode clamping is not needed if current is limited to 25ma 3k w 1k w protecting the input operating with ratiometric transducers span adjust: 0v - v in - 3v digitizing a current flow
ml2281, ml2282, ml2284, ml2288 21 applications (continued) 4maC20ma current loop converter v cc ml2281 gnd +in Cin v ref do cs clk gnd v o v cc v+ 1000pf 100k w = 50khz inp cd4024 50pf 100k w 10k w 2 3 5 68 6n139 opto coupler v cc v o 5 200k w 6.2k w 3.9k w 300k w 47k w 10k w 5k w 24k w 47 m f 10 m f 100 w + lm385C2.5v lm385C2.5v 4maC20ma 1n4148 1/6 74hc14 ?? ?? ? all power supplied by loop ? 1500v isolation at output transformer trw-tc-ssd-32 1n4148 1n4148 470 w 6v 6v 1 5 3 7 2 6 6v 10k w di 470 w 100 m f + clk v cc v cc v cc v cc ml2288 100k w 2n2222 2n2222 2 3 8 6 5 2n2222 d1 do cs v cc out 10k w cs 10k w clk 6.8k w 8 analog channels 47k w 4n28 4n28 ? no power required remotely ? 1500v isolation 6n139 high gain optocoupler 100k w isolated data converter
ml2281, ml2282, ml2284, ml2288 22 applications (continued) dq q dq q dq q s r q dsp ls193 count down ml2281 fsr start clk v in + v in C load a 5v bcd b0 clk dr do cs clk tms320 series clk 1 d7 d6 d5 d4 d3 d2 d1 d0 234567891011121314 start cs fsr do hi-z hi-z interfacing ml2281 to tms320 series sampling rate 111khz, data rate 1.33mhz
ml2281, ml2282, ml2284, ml2288 23 physical dimmensions inches (millimeters) seating plane 0.240 - 0.260 (6.09 - 6.60) pin 1 id 0.299 - 0.335 (7.59 - 8.50) 0.365 - 0.385 (9.27 - 9.77) 0.016 - 0.020 (0.40 - 0.51) 0.100 bsc (2.54 bsc) 0.008 - 0.012 (0.20 - 0.31) 0.015 min (0.38 min) 8 0o - 15o 1 0.055 - 0.065 (1.39 - 1.65) 0.170 max (4.32 max) 0.125 min (3.18 min) 0.020 min (0.51 min) (4 places) package: p08 8-pin pdip seating plane 0.148 - 0.158 (3.76 - 4.01) pin 1 id 0.228 - 0.244 (5.79 - 6.20) 0.189 - 0.199 (4.80 - 5.06) 0.012 - 0.020 (0.30 - 0.51) 0.050 bsc (1.27 bsc) 0.015 - 0.035 (0.38 - 0.89) 0.059 - 0.069 (1.49 - 1.75) 0.004 - 0.010 (0.10 - 0.26) 0.055 - 0.061 (1.40 - 1.55) 8 0.006 - 0.010 (0.15 - 0.26) 0o - 8o 1 0.017 - 0.027 (0.43 - 0.69) (4 places) package: s08 8-pin soic
ml2281, ml2282, ml2284, ml2288 24 seating plane 0.148 - 0.158 (3.76 - 4.01) pin 1 id 0.228 - 0.244 (5.79 - 6.20) 0.337 - 0.347 (8.56 - 8.81) 0.012 - 0.020 (0.30 - 0.51) 0.050 bsc (1.27 bsc) 0.015 - 0.035 (0.38 - 0.89) 0.059 - 0.069 (1.49 - 1.75) 0.004 - 0.010 (0.10 - 0.26) 0.055 - 0.061 (1.40 - 1.55) 14 0.006 - 0.010 (0.15 - 0.26) 0o - 8o 1 0.017 - 0.027 (0.43 - 0.69) (4 places) package: s14 14-pin soic physical dimmensions inches (millimeters) seating plane 0.240 - 0.260 (6.09 - 6.61) pin 1 id 0.295 - 0.325 (7.49 - 8.25) 0.740 - 0.760 (18.79 - 19.31) 0.016 - 0.022 (0.40 - 0.56) 0.100 bsc (2.54 bsc) 0.008 - 0.012 (0.20 - 0.31) 0.015 min (0.38 min) 14 0o - 15o 1 0.050 - 0.065 (1.27 - 1.65) 0.170 max (4.32 max) 0.125 min (3.18 min) 0.070 min (1.77 min) (4 places) package: p14 14-pin pdip
ml2281, ml2282, ml2284, ml2288 25 physical dimmensions inches (millimeters) seating plane 0.240 - 0.260 (6.09 - 6.61) pin 1 id 0.295 - 0.325 (7.49 - 8.26) 1.010 - 1.035 (25.65 - 26.29) 0.016 - 0.022 (0.40 - 0.56) 0.100 bsc (2.54 bsc) 0.008 - 0.012 (0.20 - 0.31) 0.015 min (0.38 min) 20 0o - 15o 1 0.055 - 0.065 (1.40 - 1.65) 0.170 max (4.32 max) 0.125 min (3.18 min) 0.060 min (1.52 min) (4 places) package: p20 20-pin pdip 0.100 - 0.110 (2.54 - 2.79) pin 1 id seating plane 0.385 - 0.395 (9.78 - 10.03) 0.350 - 0.356 (8.89 - 9.04) 0.013 - 0.021 (0.33 - 0.53) 0.165 - 0.180 (4.19 - 4.57) 1 0.350 - 0.356 (8.89 - 9.04) 0.385 - 0.395 (9.78 - 10.03) 6 11 16 0.290 - 0.330 (7.36 - 8.38) 0.025 - 0.045 (0.63 - 1.14) (radius) 0.009 - 0.011 (0.23 - 0.28) 0.026 - 0.032 (0.66 - 0.81) 0.042 - 0.048 (1.07 - 1.22) 0.042 - 0.056 (1.07 - 1.42) 0.200 bsc (5.08 bsc) package: q20 20-pin plcc 0.146 - 0.156 (3.71 - 3.96) 0.050 bsc (1.27 bsc)
ml2281, ml2282, ml2284, ml2288 26 micro linear reserves the right to make changes to any product herein to improve reliability, function or design. micro linear does not assume any liability arising out of the application or use of any product described herein, neither does it convey any license under its patent right nor the rights of others. the circuits contained in this data sheet are offered as possible applications only. micro linear makes no warranties or representations as to whether the illustrated circuits infringe any intellectual property rights of others, and will accept no responsibility or liability for use of any application herein. the customer is urged to consult with appropriate legal counsel before deciding on a particular application. 5/5/97 printed in u.s.a. ordering information alternate total temperature part number part number unadjusted error range package single analog input, 8-pin package ml2281bip (obsolete) adc0831ccn 1/2 lsb C40c to 85c plastic dip (p08) ml2281bcp adc0831bcn 0c to 70c molded dip (p08) ml2281bcs (obsolete 0c to 70c plastic soic (s08) ml2281cip (end of life) adc0831bcn 1 lsb C40c to 85c plastic dip (p08) ml2281ccp (end of life) adc0831ccn 0c to 70c molded dip (p08) ml2281ccs (end of life) 0c to 70c plastic soic (s08) two analog inputs, 8-pin package ml2282bip (obsolete) adc0832ccn 1/2 lsb C40c to 85c plastic dip (p08) ml2282bcp (obsolete) adc0832bcn 0c to 70c molded dip (p08) ml2282bcs (obsolete) 0c to 70c plastic soic (s08) ml2282cip (obsolete) adc0832bcn 1 lsb C40c to 85c plastic dip (p08) ml2282ccp (obsolete) adc0832ccn 0c to 70c molded dip (p08) ml2282ccs (obsolete) 0c to 70c plastic soic (s08) four analog inputs, 14-pin package ml2284bip (obsolete) adc0834ccn 1/2 lsb C40c to 85c plastic dip (p14) ml2284bcp (obsolete) adc0834bcn 0c to 70c molded dip (p14) ml2284bcs (obsolete) 0c to 70c plastic soic (s14) ml2284cip (obsolete) adc0834bcn 1 lsb C40c to 85c plastic dip (p14) ML2284CCP (end of life) adc0834ccn 0c to 70c molded dip (p14) ml2284ccs (obsolete) 0c to 70c plastic soic (s14) eight analog inputs, 20-pin package ml2288bip (obsolete) adc0838ccn 1/2 lsb C40c to 85c plastic dip (p20) ml2288bcp (obsolete) adc0838bcn 0c to 70c molded dip (p20) ml2288bcq (obsolete) adc0838bcv 0c to 70c molded pcc (q20) ml2288cip (obsolete) adc0838ccn 1 lsb C40c to 85c plastic dip (p20) ml2288ccp (obsolete) adc0838ccn 0c to 70c molded dip (p20) ml2288ccq (end of life) adc0838ccv 0c to 70c molded pcc (q20) 2092 concourse drive san jose, ca 95131 tel: 408/433-5200 fax: 408/432-0295 ? micro linear 1997 is a registered trademark of micro linear corporation products described in this document may be covered by one or more of the following patents, u.s.: 4,897,611; 4,964,026; 5,027,1 16; 5,281,862; 5,283,483; 5,418,502; 5,508,570; 5,510,727; 5,523,940; 5,546,017; 5,559,470; 5,565,761; 5,592,128; 5,594,376; japan: 2598946; 2619299. other patents are pending. ds2281_82_84_88-01

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